1. Field of the Invention
This invention relates to a liquid crystal monitor having a liquid crystal panel, and more particularly, to a liquid crystal monitor drive apparatus capable of reducing electromagnetic interference (hereinafter, EMI).
2. Description of the Related Art
Conventionally, a liquid crystal panel allows a picture corresponding to image signals to be displayed by controlling a light quantity passing through the panel. The liquid crystal panel provides a highly enhanced picture quality because of improvements in liquid crystal material and recent developments in the fine picture element (or pixel) treatment technique. Also, a typical liquid crystal panel is light weight, very thin, and has low power consumption requirements. Liquid crystal panels can be used for notebook computers or monitors for office automation systems. A monitor using a liquid crystal panel, hereinafter liquid crystal monitor, is driven by a drive apparatus of an analog signal system or a digital signal system, depending on whether the video signal or graphic signal is either analog or digital.
A liquid crystal monitor drive apparatus of the analog system, such as the one shown in FIG. 1, includes a signal converting stage 12 and a panel control stage 14 located between a graphic card 10 and a liquid crystal panel (not shown). The graphic card 10 is connected with the signal converting stage 12 via a first cable 16, and the signal converting stage 12 is connected to the panel control stage 14 through a second cable 18. The first and second cables 16 and 18 can be any one of serial and parallel interface types. Also, first and second cables 16 and 18 are shielded to suppress the EMI caused by radio frequency signals. The shielding of the first and second cables 16 and 18 increases the costs of the liquid crystal monitor drive apparatus.
The graphic card 10 is installed into a computer body. The graphic card 10 generates an analog graphic signal or video signal (hereinafter, analog graphic signal) to be applied to the signal converting stage 12 through the first cable 16. The graphic card 10 also supplies horizontal and vertical synchronous signals to the signal converting stage 12 through the first cable 16.
The signal converting stage 12 consists of a first connector 20, an ADC (Analog to Digital Converter) 22, a scaler 24, an LVDS (Low Voltage Differential Signaling) sender 26 and a second connector 28 connected between the first cable 16 and the second cable 18. The first connector 20 transmits the analog graphic signal from the first cable 16 to the ADC 22 as well as the horizontal and vertical synchronous signals. The ADC 22 converts the analog graphic signal into graphic data having a digital signal waveform shape. The graphic data generated at the ADC 22 includes R (red), G (Green) and B (Blue) data. The graphic data can also have 24 or 48 data bits according to a type of data bus and the ADC 22 applies the graphic data to the scaler 24 through a 24-bit or 48-bit bus. The scaler 24 varies the graphic data to match the definition and timing of the liquid crystal panel. For example, if the definition of the graphic data is higher than that of the liquid crystal panel, the scaler 24 scales down the graphic data and allows the picture corresponding to the scaled down digital graphic signal to be displayed on the liquid crystal panel. On the other hand, the scaler 24 scales up the digital graphic signal when the definition of the digital graphic signal is lower than that of the liquid crystal panel. The picture corresponding to the scaled up graphic data is then displayed on the entire or central area of the liquid crystal panel. In order to adjust the timing of the graphic data, the scaler 24 receives the horizontal and vertical synchronous signals. Also, the scaler 24 transmits the scaled graphic data to the LVDS sender 26 together with the clock signal and the horizontal and vertical synchronous signals. The LVDS sender 26 converts the parallel graphic data into serial graphic data and encodes the serial graphic data into a low voltage differential signal. The low voltage differential signal is then transmitted to the second cable 18 through the second connector 28. The LVDS sender 26 can be replaced with a panel link sender. Furthermore, the LVDS sender 26 may be replaced by a TTL (Transistor Transistor Logic) bus 26A. The TTL bus 26A transmits the original parallel graphic data from the scaler 24 to the second cable 18 through the second connector 28. Also cable 18 can be removed if the connector 28 is directly connected to the other connector 32. The signal converting stage 12 can further include a frame memory 30 connected with the scaler 24 in order to vary the frame rate of the graphic data.
Furthermore, the panel control stage 14 is composed of a third connector 32, a LVDS receiver 34 and a timing controller 36 connected serially between the second cable 18 and the liquid crystal panel. The LVDS receiver 34 inputs the low voltage differential signal, the clock signal and the horizontal and vertical synchronous signals from the second cable 18 through the third connector 32. The LVDS receiver 34 decodes the low voltage differential signal and obtains the serial graphic data. The LVDS receiver 34 also converts the serial graphic data into the parallel graphic data. The parallel graphic data generated at the LVDS receiver 34 is input into the timing controller 36 along with the clock signal and the horizontal and vertical synchronous signals. The LVDS receiver 34 can be replaced with a panel link receiver. Furthermore, the LVDS receiver 34 can be replaced by a TTL bus 34A. The TTL bus 34A transmits the original parallel graphic data from the third connector 32 to the timing controller 36. The timing controller 36 drives gate and source drive ICs (Integrated Circuits) on the liquid crystal panel and a common voltage Vcom to be applied to the liquid crystal panel, based on the graphic data, the clock signal, and the horizontal and vertical synchronous signals.
FIG. 2 illustrates a liquid crystal monitor drive apparatus of a digital system having a signal converting stage 42 and a panel control stage 44 located between a graphic card 40 and a liquid crystal panel (not shown). The graphic card 40 is connected with the signal converting stage 42 via a first cable 46, and the signal converting stage 42 is connected to the control stage 44 through a second cable 48. The first cable 46 may vary in accordance with digital interface standards (e.g., P&G, DFP, DVI and so on). The first and second cables 46 and 48 may be any one of serial and parallel interface types based on the liquid crystal panel. Also, the first and second cables 46 and 48 are shielded to suppress the EMI caused by radio frequency signals, thereby increasing the costs of the liquid crystal monitor drive apparatus. The graphic card 40, which is installed into a computer body, generates parallel graphic data and encodes the parallel graphic data including R, G, and B data into a transmittance-minimized differential signal. To this end, the graphic card 40 includes a TMDS (Transmittance-Minimized Differential Signaling) sender. The transmittance-minimized differential signal is applied to the signal converting stage 42 through the first cable 46. In addition, the graphic card 40 supplies a clock signal and horizontal and vertical synchronous signals to the signal converting stage 42 through the first cable 46.
The signal converting stage 42 consists of a first connector 50, a TMDS receiver 52, a scaler 54, a LVDS sender 56 and a second connector 58 connected between the first and second cables 46 and 48. The first connector 50 transmits the transmittance-minimized differential signal from the first cable 46 to the TMDS receiver 52 as well as the clock signal and the horizontal and vertical synchronous signals. The first connector 50 can be differed according to graphic data transmission standards. The TMDS receiver 52 inputs the transmittance-minimized differential signal, the clock signal and the horizontal and vertical synchronous signals from the first cable 46 through the first connector 50. The TMDS receiver 52 decodes the transmittance-minimized differential signal and obtains the parallel graphic data. The parallel graphic data generated at the TMDS receiver 52 is applied to the scaler 54. The graphic data decoded by the TMDS receiver 52 can have 24 or 48 data bits according to a type of data bus and the TMDS receiver 52 applies the graphic data to the scaler 54 through a 24-bit or 48-bit bus. The scaler 54 varies the definition and timing of the graphic data from the TMDS receiver 52 to match the definition and timing of the liquid crystal panel. For example, if the definition of the graphic data is higher than that of the liquid crystal panel, the scaler 54 scales down the graphic data and allows the picture corresponding to the scaled down digital graphic signal to be displayed on the liquid crystal panel. On the other hand, the scaler 54 scales up the digital graphic signal when the definition of the digital graphic signal is lower than that of the liquid crystal panel. Then, the picture corresponding to the scaled up graphic data is displayed on the entire or central area of the liquid crystal panel. In order to adjust the timing of the graphic data, the scaler 54 receives the clock signal and the horizontal and vertical synchronous signals. Also, the scaler 54 transmits the scaled graphic data to the LVDS sender 56 together with the clock signal and the horizontal and vertical synchronous signals. The LVDS sender 56 arranges the parallel graphic data into serial graphic data and encodes again the serial graphic data into a low voltage differential signal. The low voltage differential signal is transmitted to the second cable 48 through the second connector 58. Such a LVDS sender 56 can be replaced with a panel link sender. Furthermore, the LVDS sender 56 can be replaced by a TTL (Transistor Transistor Logic) bus 56A. The TTL bus 56A transmits the original parallel graphic data from the scaler 54 to the second cable 48 through the second connector 58. Also, the signal converting stage 42 can include a frame memory 60 connected with the scaler 54 in order to vary the frame rate of the graphic data.
The panel control stage 44 is composed of a third connector 62, an LVDS receiver 64 and a timing controller 66 connected serially between the second cable 48 and the liquid crystal panel. The LVDS receiver 64 inputs the low voltage differential signal, the clock signal and the horizontal and vertical synchronous signals from the second cable 48 through the third connector 62. The LVDS receiver 64 decodes the low voltage differential signal and obtains the serial graphic data. Also, the LVDS receiver 64 arranges the serial graphic data into the parallel graphic data. The parallel graphic data generated at the LVDS receiver 64 is applied to the timing controller 66 with the clock signal and the horizontal and vertical synchronous signals. The LVDS receiver 64 can be replaced with a panel link receiver. Furthermore, the LVDS receiver 64 can be replaced by a TTL bus 64A. The TTL bus 64A transmits the original parallel graphic data from the third connector 62 to the timing controller 66. The timing controller 66 drives gate and source drive ICs on the liquid crystal panel and a common voltage Vcom to be applied to the liquid crystal panel based on the graphic data, the clock signal and the horizontal and vertical synchronous signals.
As described above, the liquid crystal monitor drive apparatuses of FIGS. 1 and 2 reduce the EMI by using the LVDS sender and receiver as well as the shielding cables. However, in the liquid crystal monitor drive apparatuses of FIGS. 1 and 2, the graphic signal or data generated at the graphic card 10 or 40 must pass through a plurality of circuits to arrive at the liquid crystal panel. As a result, a great amount of wiring for radio frequency signals must be formed on a printed circuit board and in general, cables and connectors are major factors causing EMI for the liquid crystal monitor drive apparatus. Consequently, the liquid crystal monitor drive apparatus is affected by the EMI. The EMI in the liquid crystal monitor drive apparatus becomes more significant as the liquid crystal panel displays graphic data at a higher definition. For example, in the liquid crystal monitor having an SXGA class of the liquid crystal panel, the clock signal has a high frequency of 108 MHz where the frequency of the vertical synchronous signal is 60 Hz. On the other hand, if the frequency of the vertical synchronous signal is 75 Hz, the clock signal has a high frequency of 133 MHz. As a result, in the liquid crystal monitor drive apparatus for driving the SXGA class of the liquid crystal panel, the EMI becomes greater. Furthermore, if the liquid crystal monitor drive apparatus uses the LVDS sender and receiver and the shielded cables in order to suppress the EMI, the cost of the liquid crystal monitor drive apparatus increases significantly.